1. Field of the Invention
The present invention relates to a method for connecting an electronic device.
2. Related Art
In order to enhance the function of information portable apparatuses such as portable telephones and wearable computers, it is required to provide small, light and thin semiconductor packages, and modules wherein electronic devices are integrated at a high density. In a usually semiconductor package, an electrode (pad) of a semiconductor chip is connected to a package substrate via a solder bump or the like. However, since the bump exists, the semiconductor chip can not closely contact the package substrate, so that there is a problem in that it is difficult to thin the semiconductor package. In addition, there is a problem in that it is difficult to align the semiconductor chip with the package substrate.
In order to eliminate such problems, there is a method for directly forming a package wiring layer on a semiconductor chip. However, it is difficult to decrease the diameter of a via contact, and since the via contact connected to a pad is formed separately from the package wiring, the via contact is easily displaced from the package wiring. In addition, the displacement of the pad from the via contact also occurs, so that it is difficult to connect the via contact with the narrow pitch pad. Moreover, if it is failed to form a via contact or package wiring or to connect the via contact or package wiring to the pad, it is difficult to reuse (rework) the semiconductor chip.
As methods for forming a small-diameter via contact, there are proposed methods for forming a conductive column which passes thorough an insulating layer corresponding to a via contact (see, e.g. Japanese Patent Laid-Open No. 55-161306, Japanese Patent Laid-Open No. 7-207450, U.S. Pat. No. 5,498,467, and Japanese Patent Laid-Open No. 11-25755). In these methods, a conductive material, such as copper, is filled in a desired region of a porous sheet having a three-dimensional continuous hole to form a conductive column passing through the sheet from the surface to reverse thereof. In addition, Japanese Patent Application No. 11-262328 (Japanese Patent Laid-Open No. 2001-83347) proposes a method for filling a porous sheet with a conductive material in accordance with the pattern of a via contact or wiring to form a multilayer interconnection substrate.
However, the mechanical strength and dimensional stability of the porous sheet are inferior to those of a non-porous usual resin sheet. Therefore, the pattern of a via contact or wiring formed in the porous sheet is easily distorted, and the via contact or wiring is easily displaced from the pad.
As described above, in conventional methods for producing a semiconductor package, it is difficult to narrow the pitch of pads of a semiconductor chip. In addition, in a method for directly forming a package wiring layer on an electronic device, e.g. a semiconductor chip, it is difficult to rework electronic devices if displacement and so forth occur. Also in a method for forming a via contact or wiring in a porous sheet to connect it to the pad of an electronic device, the mechanical strength and dimensional stability of the porous sheet are inferior, so that there is a problem in that the displacement from the pad is easy to occur.